An MRAM is one of promising non-volatile memories, in which a digital data is stored as an orientation of a spontaneous magnetization in a ferromagnetic material. The orientation of the spontaneous magnetization is retained, unless an external magnetic field with a certain strength is applied. Therefore, the digital data stored as the orientation of the spontaneous magnetization is non-volatily stored for a long period.
According to the MRAM, magneto-resistance effects such as an AMR (Anisotropic MagnetoResistance) effect, GMR (Giant MagnetoResistance) effect and the TMR effect are utilized for reading. The reading by using the GMR effect and the reading by using the TMR effect are disclosed in Japanese Laid Open Patent Application (P2001-195878A).
The utilization of the TMR effect of these magnetoresistance effects for the reading operation is preferable in that the memory cell area of a magnetic random access memory can be made small. The U.S. Pat. No. 5,640,343 discloses an MRAM which carries out the reading operation by using the TMR effect. As shown in FIG. 1, the MRAM in the public domain includes bit lines 201, word lines 202 and memory cells 203 respective of which are provided at regions where the bit lines 201 and word lines 202 overlap.
FIG. 2 is a cross sectional view of the MRAM in the public domain. The bit line 201 is formed on a substrate 204. The bit line 201 is covered by a first interlayer insulating film 205. An aperture is formed in the first interlayer insulating film 205, and the aperture is filled in with a diode 206 and a tungsten via 207.
On the tungsten via 207, a pinned ferromagnetic layer 208, a tunnel insulating layer 209, and a free ferromagnetic layer 210 constituting the memory cell 203 are formed in order. The pinned ferromagnetic layer 208, the tunnel insulating layer 209, and the free ferromagnetic layer 210 provide the magnetic tunnel junction expressing the TMR effect. More specifically, each of the pinned ferromagnetic layer 208 and the free ferromagnetic layer 210 is made of ferromagnetic material. The pinned ferromagnetic layer 208 is formed such that the orientation of its spontaneous magnetization is along a predetermined direction, and the free ferromagnetic layer 210 is formed such that the orientation of its spontaneous magnetization is reversible. The orientation of the spontaneous magnetization in the free ferromagnetic layer 210 is allowed to be either parallel or anti-parallel to the orientation of the spontaneous magnetization in the pinned ferromagnetic layer 208. The orientations of the spontaneous magnetization in the free ferromagnetic layer 210 are associated with the data “1” and the data “0”. The tunnel insulating layer 209 is made extremely thin for the tunnel current to flow, and its thickness is typically 1 to 3 nm.
The memory cell 203 is covered by a second interlayer insulating film 211. The above-mentioned word line 202 penetrates the second interlayer insulating film 211 to be connected to the free ferromagnetic layer 210, which is not shown in FIG. 2.
FIG. 3 shows a memory cell array in which the memory cells 203 are placed and a peripheral circuit for accessing the memory cells 203. As mentioned above, the memory cells 203 are placed at the locations where the bit lines 201 and the word lines 202 cross, and the memory cells 203 electrically bridge the bit lines 201 and the word lines 202. Row selector transistors 212, 213 are connected to both ends of the bit line 201, and column selector transistors 214, 215 are connected to both ends of the word line 202.
In reference to FIG. 3, writing of data to the memory cell 203 is carried out as follows. In the case when a data is written to a memory cell 203a of the memory cells 203, a bit line 201a and a word line 202a connecting with the memory cell 203a are first selected. Row selector transistors 212a, 213a connected with the selected bit line 201a are activated. Further, column selector transistors 214a, 215a connected with the selected word line 202a are activated. A write current I1 flows in the word line 202a through the activated column selector transistors 214a, 215a. Further, a write current I2 flows in the bit line 201a through the activated row selector transistors 212a, 213a. Due to a combined magnetic field generated by the write currents I1 and I2, the free ferromagnetic layer 210 in the memory cell 203 is reversed to a desired direction and hence the data is written to the memory cell 203.
Considerably large write currents I1, I2 are necessary for reversing the spontaneous magnetization. The write currents I1, I2 are typically in a range from a few mA to a few tens of mA. Therefore, MOS transistors having large gate width are used as the row selector transistors 212, 213 and the column selector transistors 214, 215. The usage of the MOS transistors having the large gate width causes an increase of the area of the peripheral circuit of the MRAM.
On the other hand, reading of data from a memory cell 203 is carried out by detecting a read current Ir flowing through the memory cell 203 at the time when a voltage is applied between the bit line 201 and the word line 202. When the voltage is applied between the bit line 201 and the word line 202, the read current Ir flows through the tunnel insulating layer 209 of the memory cell 203 due to the tunneling phenomenon. Due to the TMR effect, the intensity of the read current Ir varies according to the orientation of the spontaneous magnetization in the free ferromagnetic layer 210. The orientation of the spontaneous magnetization in the free ferromagnetic layer 210 is detected based on the intensity of the read current Ir, and hence the data written to the memory cell 203 is identified.
One of important things in ensuring reliability of an MRAM is to prevent heat deterioration and etching damage of the memory cell 203 in the manufacturing process. Japanese Laid Open Patent Application (P2000-353791A) and the related U.S. Pat. No. 6,165,803 disclose that magnetic random access memory elements are defined by transforming portions of a magnetic element blanket layer into an insulative material in order to prevent the heat deterioration and the etching damage of the magnetic random access memory elements.
Furthermore, it is important to form the tunnel insulating layer 209 having substantially no defects for ensuring the reliability of such an MRAM. When there exist defects such as pin holes in the tunnel insulating layer 209, the bit line 201 and the word line 202 short or the performance deteriorates locally, which causes the malfunction of the MRAM.
However, the above-mentioned MRAM has a structure with which defects tend to be generated in the tunnel insulating layer 209. In the MRAM mentioned above, the pinned ferromagnetic layer 208 is formed on the tungsten via 207, and the tunnel insulating layer 209 is formed on the pinned ferromagnetic layer 208 as shown in FIG. 2. The tungsten via 207 is generally formed after a tungsten film is deposited all over the upper side of the substrate, and formed by using etch back or CMP (Chemical Mechanical Polishing) to leave the tungsten film only in the aperture provided for the first interlayer insulating film 205. In this case, the surface of the tungsten via 207 is wasted due to the etch back or the CMP. Furthermore, when the aperture provided for the first interlayer insulating film 205 is not completely filled in with the tungsten film, a concavity can be formed at the center of the tungsten via 207. Thus, it is not easy to thoroughly planarize the surface of the tungsten via 207 according to the current technology. The concavity and convexity on the surface of the tungsten via 207 cause concavity and convexity in the pinned ferromagnetic layer 208, which further cause concavity and convexity in the tunnel insulating layer 209 formed thereon. The concavity and convexity in the tunnel insulating layer 209 cause defects such as pin holes and hence cause the malfunction of the memory cell 203.
There is the necessity of eliminating defects of the tunnel insulating film as possible and preventing occurrence of failure bits.